In recent years, the performance of communication systems has reached a level where serial data is routinely sent at transmission rates in excess of 2.5 gigabits per second. To achieve these transmission rates, the signal-to-noise ratio of communication equipment is often lowered to a level where errors become significant.
Typically, communication equipment is designed to have a lower bit error rate than the maximum tolerated bit error rate of a communication system in which the communication equipment operates. For example, physical layer specifications for the Asynchronous Transfer Mode (ATM) protocol allow a maximum bit error rate of 10−10. Accordingly, the bit error rate of communication equipment is often measured both in production and in-situ to determine if the rates conform to system specifications.
Pseudo-Random Bit Sequences (PRBSs) are commonly used in Bit Error Rate (BER) measurements. Devices that perform BER measurements are often referred to as Bit Error Rate Testers (BERTs).
FIG. 1 illustrates the basic features of a communication system incorporating PRBS error measurement. The communication system 100 comprises a transmitter 110 coupled to an input of a communication channel such as a fiber optic cable 120 for transmitting a signal, and a receiver 130 coupled to an output of the communication channel 120 for receiving the signal transmitted over the communication channel 120.
PRBS error measurement is implemented in the communication system 100 using two main components: a PRBS generator 140 and a PRBS error detector 150. The PRBS generator 140 creates a signal containing PRBS data. This signal is provided to the transmitter 110, which transmits the signal over the communication channel 120. The receiver 130 receives the transmitted signal containing the PRBS data created by the PRBS generator 140, and passes the PRBS data to the PRBS error detector 150. The PRBS error detector 150 counts the number of bit errors in the PRBS data over time to determine a bit error rate.
In some systems, the signal from the PRBS generator is a baseband signal, and the transmitter 110 up-converts the baseband signal into a higher frequency transmission signal suitable for transmission over the communication channel 120. The receiver 130 then receives the transmission signal and down-converts the signal back to a baseband signal to recreate the PRBS data.
In other systems, the signal from the PRBS generator is provided at a frequency suitable for transmission over the communication channel 120. In such systems, there is no up-conversion of the signal at the transmitter, and no down-conversation of the signal at the receiver.
Reasons for using a PRBS include:                (1) the PRBS has the same statistical characteristics as a truly random bit sequence; that is, on average there are an equal number of zero value bits as one value bits. When testing communication equipment for bit errors, a truly random sequence is generally a good model for real data; and        (2) the PRBS is an algorithmically deterministic bit sequence, which means that the next bit in the sequence depends only on the state of the system generating the bit sequence; in other words, it is completely predictable. The PRBS error detector 150 uses this characteristic of the PRBS to predict the next bit in the received PRBS. Any discrepancy between the predicted next bit and the actual received next bit is detected as a bit sequence error in the PRBS error detector 150.        PRBS generators and PRBS error detectors are known, for example, from U.S. Pat. No. 6,002,714 issued to Huscroft. As shown in FIG. 2, Huscroft discloses a PRBS generator 140 comprising a seven-stage shift register 141, 142, 143, 144, 145, 146, 147 tapped at the outputs of the sixth and seventh stages 146 and 147 by an exclusive-OR gate 148. The PRBS generator 140 provides a cyclical PRBS of length 27−1 at the output 149 of the seventh stage 147.        
As shown in FIG. 3, Huscroft also discloses a PRBS error detector 150 which comprises a complementary seven-stage shift register 151, 152, 153, 154, 155, 156, 157 tapped at the output of the sixth and seventh stages 156 and 157 by a first exclusive-OR gate 158. A received PRBS is applied to the first stage 151 through an input 160. This input, and the output of the gate 158, are applied to a second exclusive-OR gate 159 to provide an error signal at an output 161.
In operation, the PRBS error detector 150 receives at the input 160 the transmitted PRBS from the PRBS generator 140. If seven sequential bits have been output by the PRBS generator 140, then the next bit output from the PRBS generator 140 will be the result of an XOR operation on the first two bits. Assuming that the seven sequential bits from the PRBS generator are then received via the input 160 of the PRBS error detector 150 without error, then the state of the seven-stage shift register in the PRBS error detector 150 will be identical to the state of the seven-stage shift register in the PRBS generator 140 just before the next bit is generated. To predict the next bit generated by the PRBS generator 140, the PRBS error detector 150 uses the gate 158 to perform an XOR operation on the first two received bits of the seven sequential bits from the PRBS generator 140. Because the PRBS error detector 150 taps the shift register at the same relative points as the PRBS generator 140, the XOR gate 158 outputs a predicted next bit, which is a prediction of the next bit that will be received from the PRBS generator 140. The XOR gate 159 performs a comparison between the predicted next bit output by the XOR gate 158, and the received next bit, which is the actual next bit received at the input 160 of the PRBS error detector 150.
If there is no error during the transmission of the actual next bit from the PRBS generator 140 then the predicted next bit will be the same value as the received actual next bit. In this case, the XOR gate 159 will generate a logical “0” output indicating no error. Conversely, if there is an error during the transmission of the actual next bit from the PRBS generator 140 then the received actual next bit will differ from the predicted next bit. In this case, the XOR gate 159 will detect the difference and will generate an output error signal, in this case a logical “1” output.
A drawback of the PRBS error detector 150 is that it assumes the portion of the PRBS stored in the seven-stage shift register contains no errors. If an error exists in any of the bits stored in the shift register then the PRBS error detector 150 will generate an erroneous predicted next bit when the erroneous bit reaches the sixth stage 156 and the seventh stage 157 of the shift register. The erroneous predicted next bit will cause the second XOR gate 159 to generate the error signal at the output of the second XOR gate 159 if the received actual next bit is correct, or to generate a no-error signal if the received actual next bit is erroneous.
If an erroneous bit is received in the PRBS error detector 150, the second XOR gate 159 will output the error signal as described above. Later, when the received erroneous bit propagates through the shift register, it will cause erroneous predictions of the predicted bit when the erroneous bit is tapped from the sixth and seventh stages 156 and 157. Assuming no further erroneous bits are received, the two erroneous predictions of the predicted bit will cause the second XOR gate 159 to generate two further error signals. Thus, for each erroneous bit received in isolation, the PRBS error detector will generate three error signals.
In the PRBS error detector 150, the bit error rate may be calculated by dividing the number of error signals received during an observation period by the length of the observation period, and then dividing that result by a factor of three to account for the three error signals generated for each received erroneous bit. However, this calculation assumes that the erroneous bits are received in isolation, that is, no more than one error bit is received every seven cycles. If erroneous bits are received more frequently than once every seven bits then there will not necessarily be three error signals produced for each received erroneous bit, and in general fewer than three error signals will be generated. For example, two consecutive erroneous bits received in the PRBS error detector 150 will produce only four error signals, two error signals fewer than if the erroneous bits had been received in isolation.
The problem of non-isolated erroneous bits in PRBS error detectors can be ignored as a statistically unlikely event. Or the problem can be solved using statistical analysis to determine the likely number of these non-isolated erroneous bits and then re-factoring the bit error rate based on the analysis. Both of these approaches assume a statistical model for distribution of error bits. Statistical models only provide estimates for the distribution of error bits, and it is therefore inevitable that the bit error rate measured using these approaches will not be completely accurate. For example, if the statistical model assumes a random distribution of error bits then error bits resulting from systematic errors in the communication channel will potentially be ignored. A further drawback with the statistical analysis approach is that it requires additional computation adding to the complexity, reliability and cost of a bit error rate tester.
From the foregoing it will be seen that there remains a need for a simple, fast, easily-realizable bit error detector that gives a correct error indication regardless of the statistical distribution of erroneous bits in a bit sequence such as a PRBS.